Fix for CRLF line endings

diff --git a/build/chimaera.img b/build/chimaera.img
index 399d6a4daed734870072e8915f8deeb3d4caf39c..22dc4e8216c8515c6ef85f20b3fe396b8ace4c87 100644 (file)
Binary files a/build/chimaera.img and b/build/chimaera.img differ

diff --git a/build/chimaera.vhd b/build/chimaera.vhd
index 05a7911bf67f529c3f7262af6603d8a1c9215e9c..f2e832a94167fbb2c102775e49ca21cbc29e1306 100644 (file)
Binary files a/build/chimaera.vhd and b/build/chimaera.vhd differ

diff --git a/src/boot/freeldr/core/ll.asm b/src/boot/freeldr/core/ll.asm
index c94b283c896cdec95db7d40195d543d0841a5301..9c0c4cbd6793b39f783ec7c2c529d27f239dce2c 100644 (file)
--- a/src/boot/freeldr/core/ll.asm
+++ b/src/boot/freeldr/core/ll.asm
@@ -346,6 +346,8 @@ _load_line:
     and     si,     si
     jz      .L12
     
+    dec     si
+    
     mov     ax,     word ptr [_load_line_data + 0]
     xor     dx,     dx
     
@@ -355,6 +357,7 @@ _load_line:
     add     ax,     si
     adc     dx,     0
     
+    inc     si
     div     cx
     
     push    es