Allow Intel 386 registers for both bits == 32 and target CPU is 386 or newer and...

diff --git a/coff.c b/coff.c
index a75afbffea19953944553b1dc43ec83efe8b593f..7c9d679a0e4a2026e606d42a562dc4aea4109222 100644 (file)
--- a/coff.c
+++ b/coff.c
@@ -40,7 +40,6 @@ static int output_relocation (FILE *outfile, struct fixup *fixup) {
         switch (fixup->reloc_type) {
         
             case RELOC_TYPE_DEFAULT:
-            case RELOC_TYPE_FAR_CALL:
             
                 switch (fixup->size) {
                 
@@ -82,12 +81,11 @@ static int output_relocation (FILE *outfile, struct fixup *fixup) {
         
         }
     
-    } else {
+    } else if (state->format == AS_OUTPUT_WIN32) {
     
         switch (fixup->reloc_type) {
         
             case RELOC_TYPE_DEFAULT:
-            case RELOC_TYPE_FAR_CALL:
             
                 switch (fixup->size) {
                 
@@ -112,6 +110,13 @@ static int output_relocation (FILE *outfile, struct fixup *fixup) {
             
             case RELOC_TYPE_RVA:
             
+                if (fixup->size != 4) {
+                            
+                    report_at (__FILE__, __LINE__, REPORT_INTERNAL_ERROR, "unsupported COFF relocation size %i for reloc_type RELOC_TYPE_RVA", fixup->size);
+                    exit (EXIT_FAILURE);
+                
+                }
+                
                 type = IMAGE_REL_I386_DIR32NB;
                 break;
             

diff --git a/intel.c b/intel.c
index e77595fdfbef4d5afe8abc4fbf12447d134bf699..27c7c6c528222dbb61ebdedbf1c58e9601ac8bd4 100644 (file)
--- a/intel.c
+++ b/intel.c
@@ -3008,22 +3008,28 @@ static int base_index_check (char *operand_string) {
             || (instruction.index_reg && (!instruction.index_reg->type.base_index || !instruction.index_reg->type.qword))) {
             goto bad;
         }
+        
+        return 0;
+    
+    }
     
-    } else if (bits == 32) {
+    if (bits == 32 || cpu_arch_flags.cpu_386) {
     
         if ((instruction.base_reg && !instruction.base_reg->type.dword) || (instruction.index_reg && (!instruction.index_reg->type.base_index || !instruction.index_reg->type.dword))) {
-            goto bad;
+            goto _check16;
         }
+        
+        return 0;
     
-    } else {
+    }
     
-        if ((instruction.base_reg && (!instruction.base_reg->type.base_index || !instruction.base_reg->type.word))
-            || (instruction.index_reg && (!instruction.index_reg->type.base_index || !instruction.index_reg->type.word
-                || !(instruction.base_reg && instruction.base_reg->number < 6 && instruction.index_reg->number >= 6
-                    && instruction.log2_scale_factor == 0)))) {
-            goto bad;
-        }
+_check16:
     
+    if ((instruction.base_reg && (!instruction.base_reg->type.base_index || !instruction.base_reg->type.word))
+        || (instruction.index_reg && (!instruction.index_reg->type.base_index || !instruction.index_reg->type.word
+            || !(instruction.base_reg && instruction.base_reg->number < 6 && instruction.index_reg->number >= 6
+                && instruction.log2_scale_factor == 0)))) {
+        goto bad;
     }
     
     return 0;